Device Feature List (DFL) defines a feature list structure that
creates a linked list of feature headers within the MMIO space
to provide an extensible way of adding features for FPGA.
Driver can walk through the feature headers to enumerate feature
devices (e.g. FPGA Management Engine, Port and Accelerator
Function Unit) and their private features for target FPGA devices.

Select this option to enable common support for Field-Programmable
Gate Array (FPGA) solutions which implement Device Feature List.
It provides enumeration APIs and feature device infrastructure.

source code:

drivers/fpga/dfl.c