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Kernel support unaligned access handling by sw
Andes processors cannot load/store information which is not
naturally aligned on the bus, i.e., a 4 byte load must start at an
address divisible by 4. On 32-bit Andes processors, these non-aligned
load/store instructions will be emulated in software if you say Y
here, which has a severe performance impact. With an IP-only
configuration it is safe to say N, otherwise say Y.
naturally aligned on the bus, i.e., a 4 byte load must start at an
address divisible by 4. On 32-bit Andes processors, these non-aligned
load/store instructions will be emulated in software if you say Y
here, which has a severe performance impact. With an IP-only
configuration it is safe to say N, otherwise say Y.