CONFIG_ARCH_WRITECOMBINE is not available for thedefaultarchitecture x86.
Result is shown for architecture loongarch
Enable WriteCombine (WUC) for ioremap()
configname: CONFIG_ARCH_WRITECOMBINE
Linux Kernel Configuration
└─>Kernel type and options
└─>Enable WriteCombine (WUC) for ioremap()
In linux kernel since version 6.2.2 (release Date: 2023-03-03)
LoongArch maintains cache coherency in hardware, but when paired
with LS7A chipsets the WUC attribute (Weak-ordered UnCached, which
is similar to WriteCombine) is out of the scope of cache coherency
machanism for PCIe devices (this is a PCIe protocol violation, which
may be fixed in newer chipsets).
This means WUC can only used for write-only memory regions now, so
this option is disabled by default, making WUC silently fallback to
SUC for ioremap(). You can enable this option if the kernel is ensured
to run on hardware without this bug.
You can override this setting via writecombine=on/off boot parameter.
with LS7A chipsets the WUC attribute (Weak-ordered UnCached, which
is similar to WriteCombine) is out of the scope of cache coherency
machanism for PCIe devices (this is a PCIe protocol violation, which
may be fixed in newer chipsets).
This means WUC can only used for write-only memory regions now, so
this option is disabled by default, making WUC silently fallback to
SUC for ioremap(). You can enable this option if the kernel is ensured
to run on hardware without this bug.
You can override this setting via writecombine=on/off boot parameter.