stable - 5.17.7
mainline - 5.15.39
mainline - 4.14.278
mainline - 5.4.193
mainline - 5.10.115
mainline - 4.9.313
mainline - 4.19.242
mainline - 5.16.20
mainline - 5.18-rc6
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CONFIG_ARM64_ERRATUM_1286807 is not available for the default architecture x86.
Result is shown for architecture arm64
Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation
Linux Kernel Configuration
└─> Kernel Features
└─> ARM errata workarounds via the alternatives framework
└─> Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation
This option adds a workaround for ARM Cortex-A76 erratum 1286807.
On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
address for a cacheable mapping of a location is being
accessed by a core while another core is remapping the virtual
address to a new physical page using the recommended
break-before-make sequence, then under very rare circumstances
TLBI+DSB completes before a read using the translation being
invalidated has been observed by other observers. The
workaround repeats the TLBI+DSB operation.
If unsure, say Y.
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