CONFIG_BF561_COREB_RESET is not available for thedefaultarchitecture x86.
Result is shown for architecture blackfin
default or selected kernelversion does not have config value CONFIG_BF561_COREB_RESET.
Result is shown for kernelversion 5.3.7
Enable Core B reset support
configname: CONFIG_BF561_COREB_RESET
Linux Kernel Configuration
└─>BF561 Specific Configuration
└─>Core B Support
└─>Enable Core B reset support
In linux kernel since version 2.6.22 (release Date: 2007-07-08)
This requires code in the application that is loaded
into Core B. In order to reset, the application needs
to install an interrupt handler for Supplemental
Interrupt 0, that sets RETI to 0xff600000 and writes
bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0.
This causes Core B to stall when Supplemental Interrupt
0 is set, and will reset PC to 0xff600000 when
COREB_SRAM_INIT is cleared.
into Core B. In order to reset, the application needs
to install an interrupt handler for Supplemental
Interrupt 0, that sets RETI to 0xff600000 and writes
bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0.
This causes Core B to stall when Supplemental Interrupt
0 is set, and will reset PC to 0xff600000 when
COREB_SRAM_INIT is cleared.